View SY89871U07_5045509.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Micrel, Inc.
2.5GHz ANY DIFF. IN-TO-LVPECL SY89871U Precision Edge(R) PROGRAMMABLE CLOCK DIVIDER/ SY89871U FANOUT BUFFER W/INTERNAL TERMINATION
Precision Edge(R)
FEATURES
Two matched-delay outputs: * Bank A: undivided pass-through (QA) * Bank B: programmable divide by 2, 4, 8, 16 (QB0, QB1) Matched delay: all outputs have matched delay, independent of divider setting Guaranteed AC performance: * >2.5GHz fMAX * <250ps tr/tf * <670ps tpd (matched delay) * <15ps within-device skew Low jitter design * <1psRMS cycle-to-cycle jitter * <10psPP total jitter Power supply 3.3V or 2.5V Unique patent-pending input termination and VT pin for DC- and AC-coupled inputs: any differential inputs (LVPECL, LVDS, CML, HSTL) TTL/CMOS inputs for select and reset 100K EP compatible LVPECL outputs Parallel programming capability Wide operating temperature range: -40C to +85C Available in 16-pin (3mm x 3mm) MLF(R) package Precision Edge(R)
DESCRIPTION
The SY89871U is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed differential clock input (AC or DC-coupled) CML, LVPECL, HSTL or LVDS clock input signal and dividing down the frequency using a programmable divider ratio to create a frequencylocked lower speed version of the input clock (Bank B). Available divider ratios are 2, 4, 8 and 16. In a typical 622MHz clock system this would provide availability of 311MHz, 155MHz, 77MHz, or 38MHz auxiliary clock components. The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards. A VREF-AC reference is included for AC-coupled applications. The SY89871U includes two phase-matched output banks. Bank A (QA) is a frequency-matched copy of the input. Bank B (QB0, QB1) is a divided down output of the input frequency. Bank A and Bank B maintain a matched delay independent of the divider setting. All support documentation can be found on Micrel's web site at: www.micrel.com.
APPLICATIONS
OC-3 to OC-192 SONET/SDH applications Transponders Oscillators SONET/SDH line cards
FUNCTIONAL BLOCK DIAGRAM
QA
VREF-AC
TYPICAL PERFORMANCE
/QA
QA@622MHz and QB@155.5MHz
QA
QB0
IN 50 VT 50 /IN Divided by 2, 4, 8 or 16
/QB0
622MHz Output
/QA
QB1 /QB1
QB0
S0 Decoder S1
155.5MHz Output
/4
/QB0
/RESET
Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. M9999-082407 hbwhelp@micrel.com or (408) 955-1690
Rev.: F Amendment: /0
1
Issue Date: August 2007
Micrel, Inc.
Precision Edge(R) SY89871U
PACKAGE/ORDERING INFORMATION
GND VCC S0 S1
Ordering Information
Part Number
12 11 10 9
16
15
14
13
Package Operating Type Range MLF-16 MLF-16 MLF-16 MLF-16 Industrial Industrial Industrial Industrial
Package Marking 871U 871U 871U with Pb-Free bar line indicator 871U with Pb-Free bar line indicator
Lead Finish Sn-Pb Sn-Pb NiPdAu Pb-Free NiPdAu Pb-Free
QB0 /QB0 QB1 /QB1
1 2 3 4 5 6 7 8
IN VT VREF-AC /IN
SY89871UMI SY89871UMITR(1) SY89871UMG(2) SY89871UMGTR(1, 2)
/QA
QA
/RESET
VCC
16-Pin MLF(R) (MLF-16)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
PIN DESCRIPTION
Pin Number 1, 2, 3, 4 Pin Name QB0, /QB0 QB1, /QB1 QA, /QA VCC /RESET IN, /IN VREF-AC Pin Function Differential Buffered Output Clocks: This differential output is a divided-down version of the input frequency and has a matched output delay with Bank A. Divided by 2, 4, 8, or 16. See "Truth Table." Unused output pairs may be left floating. Differential Buffered Undivided Output Clock. Positive Power Supply: Bypass with 0.1FTMTM0.01F low ESR capacitors. Output Reset: Internal 25ky pull-up. Logic LOW will reset the divider select. See "Truth Table." Input threshold is VCC/2. Differential Input: Internal 50y termination resistors to VT input. See "Input Interface Applications" section. Reference Voltage: Equal to VCC-1.4V (approx.), and used for AC-coupled applications. For DC-coupled applications, VREF-AC is normally left floating. Maximum sink/source current is 0.5mA. See "Input Interface Applications" section. Input Termination Center-Tap: Each side of differential input pair terminates to this pin. The VT pin provides a center tap to a termination network for maximum interface flexibilty. For CML and LVDS inputs, leave this pin floating. See "Input Interface Application" section. Ground. Select Pins: See "Truth Table." LVTTL/CMOS logic levels. Internal 25ky pull-up resistor. Logic HIGH if left unconnected (divided by 16 mode). S0 = LSB. Input threshold is VCC/2.
5, 6 7, 14 8 12, 9 10
11
VT
13 15, 16
GND S1, S0
TRUTH TABLE
/RESET 1 1 1 1 0 S1 0 0 1 1 X S0 0 1 0 1 X Bank A Output Input Clock Input Clock Input Clock Input Clock Input Clock Bank B Outputs Input Clock /2 Input Clock /4 Input Clock /8 Input Clock /16 QB = LOW, /QB = HIGH
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89871U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ................................... -0.5V to +4.0V Input Voltage (VIN) ............................... -0.5V to VCC +0.3V PECL Output Current (IOUT) Continuous .......................................................... 50mA Surge .................................................................100mA VT Current (IVT) ...................................................... 100mA Input Current IN, /IN (IIN) .......................................... 50mA VREF-AC Sink/Source Current (IVREF-AC) .................... 2mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ........................ -65C to +150C
Operating Ratings(2)
Supply Voltage (VCC) ............................. +2.375V to +3.63V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance(3) MLF(R) (JA) Still-Air ............................................................. 60C/W 500lfpm ........................................................... 54C/W MLF(R) (JB) Junction-to-board ............................................ 38C/W
DC ELECTRICAL CHARACTERISTICS(4)
TA = -40C to +85C, unless otherwise stated. Symbol VCC ICC RIN VIH VIL VIN VDIFF_IN |IIN| VREF-AC
Notes: 1. Permanent device damage may occur if ratings in the "Absolute Maximum Ratings" section are exceeded. This is a stress rating only and functional operation is not implied for conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Junction-to-board resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. 4. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 5. See "Timing Diagram" for VIN definition. VIN (max.) is specified when VT is floating. 6. See "Typical Operating Characteristics" section for VDIFF definition. 7. Due to the internal termination (see "Input Buffer Structure" section) the input current depends on the applied voltages at IN, /IN and VT inputs. Do not apply a combination of voltages that causes the input current to exceed the maximum limit!
Parameter Power Supply Voltage Power Supply Current Differential Input Resistance, (IN-to-/IN) Input HIGH Voltage, (IN, /IN) Input LOW Voltage, (IN, /IN) Input Voltage Swing Differential Input Voltage Swing Input Current, (IN, /IN) Reference Voltage
Condition
Min 2.37
Typ
Max 3.60
Units V mA y V V V V
No load, max VCC. 90 0.1 -0.3 Notes 5 Notes 5, 6 Note 7 0.1 0.2
50 100
75 110 VCC+0.3 VIH-0.1 VCC
45 VCC-1.525 VCC-1.425 VCC-1.325
mA V
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
3
Micrel, Inc.
Precision Edge(R) SY89871U
(100KEP) LVPECL DC ELECTRICAL CHARACTERISTICS(8)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C, RL = 50y to VCC -2V, unless otherwise stated. Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing Condition Min Typ Max Units V V mV V
VCC-1.145 VCC-1.020 VCC-0.895 VCC-1.945 VCC-1.820 VCC-1.695 550 1.10 800 1.6 1050 2.1
LVTTL/LVCMOS DC ELECTRICAL CHARACTERISTICS(8)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C. Symbol VIH VIL IIH IIL
Note: 8. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. Parameters are for VCC = 2.5V. They vary 1:1 with VCC.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max
Units V
0.8 -125 20 -300
V A A
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY89871U
AC ELECTRICAL CHARACTERISTICS(9)
VCC = 3.3V 10% or 2.5V 5%; TA = -40C to +85C, unless otherwise stated. Symbol fMAX tPD tSKEW Parameter Maximum Output Toggle Frequency Maximum Input Frequency Differential Propagation Delay IN-to-QA or QB Within-Device Skew (Differential) QB0-to-QB1 Within-Device Skew (Differential) QA-to-QB Part-to-Part Skew (Differential) tJITTER tRR tr, tf
Notes: 9. Measured with 400mV input signal, 50% duty cycle, all loading with 50y to VCC-2V, unless otherwise stated. 10. Bank A (pass-through) maximum frequency is limited by the output stage. Bank B (input-to-output /2, /4, /8, /16) can accept an input frequency >3GHz, while Bank A will be slew rate limited. 11. Skew is measured between outputs under identical transitions. 12. Cycle-to-cycle jitter definition: the variation in period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_cc =Tn-Tn+1, where T is the time between rising edges of the output signal. 13. Total jitter definition: with an ideal clock input, of frequency - fMAX (device), no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value.
Condition Output Swing 400mV Note 10 Input Swing < 400mV Input Swing 400mV Note 11 Note 11 Note 11 Note 12 Note 13
Min 2.5 3.2 460 420
Typ
Max
Units GHz GHz
580 550 7 12
710 670 15 30 250 1 10
ps ps ps ps ps psRMS psPP ps ps
Cycle-to-Cycle Jitter Total Jitter Reset Recovery Time Output Rise/Fall Times (20% to 80%)
600 70 150 250
TIMING DIAGRAM
VCC/2 /RESET tRR IN /IN VIN Swing /QB VOUT Swing QB tPD
QA /QA
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
5
Micrel, Inc.
Precision Edge(R) SY89871U
TYPICAL OPERATING CHARACTERISTICS
VCC = 3.3V, VIN = 400mV, TA = 25C, RL = 50y to VCC-2V, unless otherwise stated.
QA Output Amplitude vs. Frequency
900
PROPAGATION DELAY (ps) 900 800 700 600 500 400 300 200 100 0 0 200 400 600 800 1000 1200 INPUT SWING (mV)
IN to Q Propagation Delay vs. Input Swing
700
IN to Q Propagation Delay vs. Temperature
PROPAGATION DELAY (ps)
800
QA AMPLITUDE (mV)
700 600 500 400 300 200 100
0 1000 1500 2000 2500 3000 3500 500
600
500
400
0
300 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (C)
FREQUENCY (MHz)
QA@622MHz and QB@155.5MHz 622MHz Output
QA
1.25GHz Output
/Q
Output Swing (200mV/div.)
QB0
155.5MHz Output
/4
Output Swing (100mV/div.)
Q
/QA
/QB0 TIME (1ns/div.)
TIME (100ps/div.)
2.5GHz Output
/Q
Output Swing (100mV/div.)
Q
TIME (100ps/div.)
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
6
Micrel, Inc.
Precision Edge(R) SY89871U
DEFINITION OF SINGLE-ENDED AND DIFFERENTIAL SWING
VIN, VOUT 800mV (typical)
VDIFF_IN, VDIFF_OUT 1600mV (typical)
Figure 1a. Single-Ended Swing
Figure 1b. Differential Swing
INPUT BUFFER STRUCTURE
VCC
VCC
1.86k
1.86k
25k S0 S1 /RESET
R
1.86k IN 50 VT 50 /IN GND
1.86k
R
SY89871U GND
Figure 2a. Simplified Differential Input Buffer
Figure 2b. Simplified TTL/CMOS Input Buffer
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
7
Micrel, Inc.
Precision Edge(R) SY89871U
INPUT INTERFACE APPLICATIONS
VCC VCC
VCC
VCC
VCC
VCC
PECL
IN /IN VCC GND 0.01F VT Rpd VREF-AC NC Note: For 3.3V, Rpd = 50. For 2.5V, Rpd = 19. SY89871U
IN CML /IN SY89871U GND NC NC VT VREF-AC 0.01F GND VCC CML
IN /IN SY89871U VT VREF-AC
Figure 3a. DC-Coupled CML Input Interface
Figure 3b. AC-Coupled CML Input Interface
Figure 3c. DC-Coupled PECL Input Interface
VCC
VCC
VCC VCC
IN PECL /IN Rpd Rpd VCC GND GND 0.01F Note: For 3.3V, Rpd = 100. For 2.5V, Rpd = 50. VT VREF-AC SY89871U
VCC
VCC
IN LVDS /IN SY89871U GND
IN HSTL /IN SY89871U GND VT NC GND VREF-AC
NC NC
VT VREF-AC
Figure 3d. AC-Coupled PECL Input Interface
Figure 3e. LVDS Input Interface
Figure 3f. HSTL Input Interface
RELATED PRODUCT AND SUPPORT DOCUMENTATION
Part Number SY89874U Function 2.5GHz Any Diff. In-to-LVPECL Programmable Clock Divider and 1:2 Fanout Buffer w/Internal Termination MLF(R) Application Note HBW Solutions New Products and Applications Data Sheet Link http://www.micrel.com/product-info/products/sy89874u.shtml
http://www.amkor.com/products/notes_papers/mlf_appnote.pdf http://www.micrel.com/product-info/products/solutions.shtml
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
8
Micrel, Inc.
Precision Edge(R) SY89871U
LVPECL OUTPUT TERMINATION RECOMMENDATIONS
+3.3V
+3.3V
ZO = 50 ZO = 50
R1 130
R1 130
+3.3V
R2 82
R2 82
Vt = VCC --2V
Figure 4a. Parallel Termination-Thevenin Equivalent
Note: 1. For +2.5V systems: R1 = 250y, R2 = 62.5y.
+3.3V
Z = 50 Z = 50 50 50
+3.3V
"source" 50 Rb
"destination"
VCC
C1 (optional) 0.01F
Figure 4b. Three-Resistor "Y-Termination"
Notes: 1. Power-saving alternative to Thevenin termination. 2. Place termination resistors as close to destination inputs as possible. 3. Rb resistor sets the DC bias voltage, equal to VT. For +3.3V systems Rb = 46y to 50y. For +2.5V systems Rb = 19y. 4. C1 is an optional bypass capacitor intended to compensate for any tr/tf mismatches.
+3.3V R1 130 ZO = 50 /Q Vt = VCC --2V R2 82
+3.3V R1 130 Vt = VCC --1.3V R3 +3.3V 1k
+3.3V
Q
R4 1.6k R2 82
Figure 4d. Terminating Unused I/O
Notes: 1. Unused output (/Q) must be terminated to balance the output. 2. For +2.5V systems: R1 = 250y, R2 = 62.5y, R3 = 1.25ky, R4 = 1.2ky.
M9999-082407 hbwhelp@micrel.com or (408) 955-1690
9
Micrel, Inc.
Precision Edge(R) SY89871U
16-PIN MicroLeadFrame(R) (MLF-16)
Package EP- Exposed Pad
Die
CompSide Island
Heat Dissipation Heat Dissipation VEE Heavy Copper Plane VEE Heavy Copper Plane
PCB Thermal Consideration for 16-Pin MLF(R) Package (Always solder, or equivalent, the exposed pad to the PCB) Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry-pack form. 2. Exposed pads must be soldered to a ground for proper thermal management.
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-082407 hbwhelp@micrel.com or (408) 955-1690
10

▲Up To Search▲

Price & Availability of SY89871U07

	To Download SY89871U07 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .